1. Field of the Invention
The present invention relates to a semiconductor memory device for carrying out high-speed read-out of data recorded in memory cells.
2. Description of the Related Art
In general, [0]/[1] binary information, or multi-value information expressed by the voltage level of a gate that employs threshold control to turn a transistor ON/OFF, can be stored in a single transistor in a semiconductor memory device such as a ROM (read only memory).
A plurality of memory cell transistors are formed to a matrix on the semiconductor substrate in the aforementioned semiconductor memory device. Word lines formed in patterns in the matrix rows are connected to a gate, while bit lines formed in patterns in matrix columns are connected to a drain.
When reading out data stored in the memory cells of this semiconductor memory device, the memory cell corresponding to the inputted address signal is selected according to which word and bit lines are activated by decoders. The data recorded in the memory cell corresponding to address is read out by comparing the current flowing to the selected memory cell transistor with the current flowing to a reference memory cell at a sense amplifier.
In the above-described semiconductor memory device, each memory cell transistor is formed to be isolated from the other memory cell transistors on the semiconductor substrate by use of an element separating film. The drain for the memory cell transistor is connected to the bit line, and the source is grounded.
A simple design may be employed for the circuitry required for read out in the semiconductor memory device design as described above. However, for each memory cell transistor, it is necessary to form a contact to the diffusion layer comprising the drain, this contact connecting the diffusion layer and the bit line to be wired. Because of this need to form a contract to the drain diffusion layer, a larger area must be employed for the diffusion layer than would otherwise be required in the transistor design. It therefore becomes difficult to increase the degree of integration in the memory cell transistor of the above-described design.
In order to resolve the deficits present in the structure of this memory cell transistor, it has become the practice to employ a virtual grounding type memory cell transistor design and arrangement that increases the degree of integration in the memory cell.
In other words, a design (sub-bit line, virtual sub-grounding line) is employed in which a common diffusion layer is used to form the drain and source for memory cell transistors that are adjacent to one another in a row, and these diffusion layers are connected in the columns. As a result, each diffusion layer is connected on the matrix, and it is no longer necessary to provide a contact to the area in which the memory cells are formed. Thus, the degree of integration in this memory cell transistor can be increased as compared to the case in which a contact is formed.
The conventional semiconductor memory device employing a virtual grounding type memory cell transistor design as described above will now be explained using FIGS. 13 and 14. FIG. 13 is a block diagram showing the structure of a conventional semiconductor memory device. FIG. 14 is a conceptual diagram showing the detailed structure of memory cell 16 in FIG. 13.
In FIG. 13, data is stored in memory cell transistors that form a memory cell area 16B in memory cell 16. An address AD is input from an external CPU (central processing unit) or the like, specifying a memory cell transistor within memory cell area 16B. The data stored in this memory cell transistor is then read out as a result.
Address buffer 11 performs waveform shaping of the inputted address signal AD, and, after holding the signal, outputs it to Y decoder 12, bank decoder 13, X decoder 4 and virtual GND selector 15. X decoder 4 decodes part of the plurality of bits in the address AD signal, and selects and activates one word line selection signal from among word line selection signal WD0.about.word line selection signal WDn. As a result, all the memory cell transistors in one row of the memory cell array in memory cell area 16B are selected together, and a data read out state is enabled.
Y decoder 12 decodes part of the plurality of bits in the address signal AD, and outputs Y decoder signal YD to Y selector 17. Based on the inputted Y decoder signal YD, Y selector 17 selects one main bit line from among main bit line D1.about.main bit line D1 that are connected to each memory cell transistor in memory cell 16.
As a result, a main bit line is connected to sense amplifier circuit 9, and a read out state is enabled for the memory cell transistor that corresponds to address signal AD. As a result, Y selector 17 inputs the data stored in this selected memory cell transistor via the main bit line, and outputs the data to sense amplifier circuit 9 as a data signal DG.
At this time, the memory cell transistor performs data storage by changing the threshold voltage, which is under ON/OFF control. In other words, when the threshold voltage is changed so that the word selection line that is connected to the gate is activated and the memory cell transistor enters the ON state, data is stored by means of the flow of current proportionate to this threshold value. In the case of binary information, two thresholds, i.e., a state in which current flows easily and a state in which current does not flow easily, are controlled.
Sense amplifier circuit 9 compares the current of this input data signal DG and the current of a reference signal RG that is input from reference circuit 10. If the current of data signal DG is smaller than the current of reference signal RG at this time for example, then the current state is one in which the threshold value is high and current does not readily flow. Therefore, the data stored in the memory cell transistor is [H]. Conversely, if the current of the data signal DG is larger than the current of the reference signal RG, then the data stored in the memory cell transistor is [L].
Next, sense amplifier circuit 9 outputs the results of this comparison of the currents as data signal D0.
Reference circuit 10 is formed of a constant voltage circuit (a voltage stabilizer) that outputs a voltage level which is intermediate between the voltage level of the bit signal when the data stored in the memory cell transistor in memory cell area 16B is [H], and the voltage level of the bit signal when the data stored in the memory cell transistor in memory cell area 16B is [L].
In addition, for example, reference circuit 10 may also have a design in which a reference transistor is employed that is controlled by a threshold value where the voltage level of reference signal RG, which is selected by the word selection line and determined by the current flow, assumes a voltage level that is intermediate between the bit signal voltage level when the data stored in the memory cell transistor is [H] and the bit signal voltage level when the data stored in the memory cell transistor is [L].
Precharge circuit 8 prevents the flow of current to memory cell transistors other than the one selected, by means of impressing a bias voltage onto the main bit lines that are connected to the non-selected memory cell transistors that are adjacent to the memory cell transistor within memory cell area 16B that was selected by the address signal AD.
The bias voltage supplied from precharge circuit 8 at this time is output as precharge signal PC to the main bit line that was selected by Y selector 17 in accordance with address signal AD.
Bank decoder 13 decodes a portion of address signal AD, and outputs bank selection signal BS0.about.bank selection signal BS3 as the decoded results to the bank selection signal lines corresponding respectively to bank selector 16A and bank selector 16C. Bank selection signal BS0 and bank selection signal BS1 are output to the bank selection signal line of bank selector 16A, while bank selection signal BS2 and bank selection signal BS3 are output to the bank selection signal line of bank selector 16C.
Based on address signal AD from address buffer 11, virtual GND selector 15 selects one virtual main grounding line from among virtual main grounding line V1.about.virtual main grounding line Vk that are connected to the memory cell transistors in memory cell array 16B, and designates this as the grounding potential GND. Virtual GND selector 15 supplies a specific bias voltage Vp (the same potential as that of the main bit line connected to sense amplifier circuit 9, for example) to the virtual main grounding lines that were not selected, or places these unselected virtual main grounding lines in the OPEN state. "OPEN state" as employed here means a state in which the line is not connected to voltage or current sources.
Next, memory cell 16 will be explained in detail using FIG. 14. FIG. 14 is a conceptual diagram showing the structure of memory cell 16, and excludes areas related to main bit line D1.about.main bit line D3 and virtual main grounding line V1.about.virtual main grounding line V3. In this figure, bank selector 16A is formed of MOS transistor BT00, MOS transistor BT01, MOS transistor BT10, MOS transistor BT11, MOS transistor BT20, and MOS transistor BT21. Similarly, bank selector 16C is formed of a MOS transistor BT02, MOS transistor BT03, MOS transistor BT12, MOS transistor BT13, MOS transistor BT22, and MOS transistor BT23.
The drain of MOS transistor BT00 and MOS transistor BT01 is connected to metal wire ML1 (main bit line D1) via a contact CT1. The gate of MOS transistor BT00 is connected to the bank selection signal line of bank selection signal BS0, and the source is connected to the source and the drain of a memory cell transistor in memory cell array 16B via sub-bit line B00. In addition, the gate of MOS transistor BT01 is connected to the bank selection signal line of bank selection signal BS1, and the source is connected to the source and the drain of a memory cell transistor in memory cell array 16B via sub-bit line B01.
The drain of MOS transistor BT10 and MOS transistor BT11 is connected to metal wire ML3 (main bit line D2) via contact CT3. The gate of MOS transistor BT10 is connected to the bank selection signal line of bank selection signal BS0, and the source is connected to the source and the drain of a memory cell transistor in memory cell array 16B via sub-bit line B10. The gate of MOS transistor BT11 is connected to the bank selection signal line of bank selection signal BS1, and the source is connected to the source and the drain of a memory cell transistor in memory cell array 16B via sub-bit line B11.
The drain of MOS transistor BT20 and MOS transistor BT21 is connected to metal wire ML5 (main bit line D3) via a contact CT5. The gate of MOS transistor BT20 is connected to the bank selection signal line of bank selection signal BS0, and the source is connected to the source and the drain of a memory cell transistor in memory cell array 16B via sub-bit line B20. In addition, the gate of MOS transistor BT21 is connected to the bank selection signal line of bank selection signal BS1, and the source is connected to the source and the drain of a memory cell transistor in memory cell array 16B via sub-bit line B21.
The source of MOS transistor BT02 and MOS transistor BT03 is connected to metal wire ML0 (virtual main grounding line V1) via contact CT0. The gate of MOS transistor BT02 is connected to the bank selection signal line of bank selection signal BS2, and the drain is connected to the source and the drain of a memory cell transistor in memory cell array 16B via virtual sub-grounding line B02. The gate of MOS transistor BT03 is connected to the bank selection signal line of bank selection signal BS3, and the source is connected to the source and drain of a memory cell transistor in memory cell array 16B via virtual sub-grounding line B03.
The source of MOS transistor BT12 and MOS transistor BT13 is connected to metal wire ML2 (virtual main grounding line V2) via contact CT2. The gate of MOS transistor BT12 is connected to the bank selection signal line of bank selection signal BS2, and the drain is connected to the source and drain of a memory cell transistor in memory cell array 16B via virtual sub-grounding line B12. The gate of MOS transistor BT13 is connected to the bank selection signal line of bank selection signal BS3, and the source is connected to the source and drain of a memory cell transistor in memory cell array 16B via virtual sub-grounding line B13.
The source of MOS transistor BT22 and MOS transistor BT23 is connected to metal wire ML4 (virtual main grounding line V4) via contact CT4. The gate of MOS transistor BT22 is connected to the bank selection signal line of bank selection signal BS2, and the drain is connected to the source and drain of a memory cell transistor in memory cell array 16B via virtual sub-grounding line B22. The gate of MOS transistor BT23 is connected to the bank selection signal line of bank selection signal BS3, and the source is connected to the source and drain of a memory cell transistor in memory cell array 16B via virtual sub-grounding line B23.
Next, patterns will be shown for the potential that is impressed on main bit line D1.about.main bit line D3, and virtual main grounding line V1.about.virtual main grounding line V3 during respective reading out of memory cell transistor M0, memory cell transistor M1, memory cell transistor M2, and memory cell transistor M3 in a conventional semiconductor memory device.
When reading out data stored in any one of the memory transistors in memory cell array 16B, one of the following four impression potential patterns results.
The memory cell transistors and MOS transistors will all be explained below as n channel MOS transistors.
a. First Impression Pattern (Read Out of Memory Cell Transistor M0)
In order to sense the current flowing to memory cell transistor M0, the following impression pattern is employed so that current does not flow to other memory cell transistors from the metal wire ML3 (main bit line D2) that is connected to sense amplifier circuit 9.
For example, as shown in FIG. 15, in accordance with the data in address AD for selecting cell transistor M0 and based on Y decoder signal YD input from Y decoder 12, Y selector 17 places metal wire ML1 (main bit line D1) in the OPEN state, thereby connecting metal wire ML3 (main bit line D2) and sense amplifier circuit 9. In addition, similarly, the Y selector impresses a specific bias voltage Vp onto metal wire ML5 (main bit line D3) based on Y decoder signal YD.
In accordance with the data in address AD for selecting cell transistor M0, virtual GND selector 15 places metal wire ML0 (virtual main grounding line V1) in the OPEN state, designates metal wire ML2 (virtual main grounding line V2) as grounding potential GND, and sets metal wire ML4 (virtual main grounding line V3) to a specific bias voltage Vp.
Next, in accordance with the data in address AD for selecting cell transistor M0, bank decoder 13 sets bank selection signal BS0 and bank selection signal BS2 to [H] level. As a result, MOS transistor BT00, MOS transistor BT10, MOS transistor BT21, MOS transistor BT02, MOS transistor BT12, and MOS transistor BT22 enter the ON state.
As a result, the drain of memory cell transistor M0 is connected to metal wire ML3 (main bit line D2) via MOS transistor BT10. The source of memory cell transistor M0 is connected to metal wire ML2 (virtual main grounding line V2 which assumes grounding potential GND) via MOS transistor BT12.
Next, in accordance with the data in address AD for selecting cell transistor M0, X decoder 4 sets word line WD2 to [H] level. As a result, all memory cell transistors for which the gate is connected to word line WD2 enter the ON state, these including memory cell transistor M0, memory cell transistor M1, memory cell transistor M2, and memory cell transistor M3.
However, the source and drain of the memory cell transistor which is connected to the source of memory cell transistor M0, i.e., the memory cell transistor which is positioned to the left of virtual sub-grounding line B12 to which metal wire ML2 (virtual main grounding line V2), forming grounding potential GND, is connected, is placed in the OPEN state. For this reason, current flows via virtual sub-grounding line B12 from the source of memory cell transistor M0 to metal wire ML2 (virtual main grounding line V2) only.
In addition, the source and drain of the memory cell transistor which is connected to the drain of memory cell transistor M0, i.e., the memory cell transistor which is positioned to the right of sub-bit line B10 to which metal wire ML3 (main bit line D2), connected to sense amplifier circuit 9, is connected, becomes a specific potential Vp. For this reason, current from the metal wire ML2 connected to sense amplifier circuit 9 flows into the drain of memory cell transistor M0 only.
As explained above, in accordance with the data in address AD for selecting memory cell transistor M0, Y decoder 12, bank decoder 13, Y selector 17 and virtual GND selector 15 carry out processing so that the current from sense amplifier circuit 9 flows only to memory cell transistor M0. As a result, the data stored in memory cell transistor M0 is accurately read out.
b. Second Impression Pattern (Read Out of Memory Cell Transistor M1)
In order to sense the current flowing to memory cell transistor M1, the following impression pattern is established so that current does not flow to other memory cell transistors from the metal wire ML3 (main bit line D2) which is connected to sense amplifier circuit 9.
For example, as shown in FIG. 16, in accordance with the data in address AD for selecting cell transistor M1 and based on Y decoder signal YD input from Y decoder 12, Y selector 17 places metal wire ML5 (main bit line D3) in the OPEN state, and connects metal wire ML3 (main bit line D2) and sense amplifier circuit 9. In addition, similarly, the Y selector impresses a specific bias voltage Vp onto metal wire ML1 (main bit line D1) based on Y decoder signal YD.
Then, in accordance with the data in address AD for selecting cell transistor M1, virtual GND selector 15 places metal wire ML4 (virtual main grounding line V3) in the OPEN state, designates metal wire ML2 (virtual main grounding line V2) as the grounding potential GND, and sets metal wire ML0 (virtual main grounding line V1) to a specific bias voltage Vp.
In accordance with the data in address AD for selecting cell transistor M1, bank decoder 13 sets bank selection signal BS0 and bank selection signal BS3 to [H] level. As a result, MOS transistor BT00, MOS transistor BT10, MOS transistor BT20, MOS transistor BT03, MOS transistor BT13 and MOS transistor BT23 are placed in the ON state.
As a result, the drain for memory cell transistor M1 is connected to metal wire ML3 (main bit line D2) via MOS transistor BT10. In addition, the source of memory cell transistor M1 is connected to metal wire ML2 (virtual main grounding line V2 which becomes grounding potential GND) via MOS transistor BT13.
Next, X decoder 4 sets word line WD2 to [H] level in accordance with the data in address AD for selecting cell transistor M1. As a result, all memory cell transistors for which the gate is connected to word line WD2 enter the ON state, these including memory cell transistor M0, memory cell transistor M1, memory cell transistor M2 and memory cell transistor M3.
However, the source and drain for the memory cell transistor positioned to the right of virtual sub-grounding line B13 which is connected to the source of memory cell transistor M1, i.e., to which metal wire ML2 (virtual main grounding line V2), forming grounding potential GND, is connected, enter the OPEN state. For this reason, current flows from the source of memory cell transistor M1 via virtual sub-grounding line B13 into metal wire ML2 (virtual main grounding line V2) only.
The source and drain for the memory cell transistor positioned to the left of sub-bit line B10 which is connected to the drain of memory cell transistor M1, i.e., to which metal wire ML3 (main bit line D2), connected to sense amplifier circuit 9, is connected, become a specific potential Vp. For this reason, the current that flows from metal wire ML3 (main bit line D2) that is connected to sense amplifier circuit 9 flows into the drain of memory cell transistor M1 only.
As described above, in accordance with the data in address AD for selecting memory cell transistor M1, Y decoder 12, bank decoder 13, Y selector 17 and virtual GND selector 15 operate so that the current from sense amplifier circuit 9 flows into memory cell transistor M1 only. As a result, the data stored in memory cell transistor M1 can be accurately read out.
c. Third Impression Pattern (Read Out of Memory Cell Transistor M2)
In order to sense the current flowing to memory cell transistor M2, the following impression pattern is established so that current does not flow to other memory cell transistors from metal wire ML3 (main bit line D2) that is connected to sense amplifier circuit 9.
As shown in FIG. 17 for example, the voltage impression pattern between main bit line D1.about.main bit line D3 and virtual main grounding line V1.about.virtual main grounding line V3 is equivalent to the second impression pattern shown in FIG. 2. Accordingly, an explanation thereof will be omitted.
Then, in accordance with the data in address AD for selecting cell transistor M2, bank decoder 13 sets the bank selection signal BS1 and bank selection signal BS3 to [H] level. As a result, MOS transistor BT01, MOS transistor BT11, MOS transistor BT21, MOS transistor BT03, MOS transistor BT13 and MOS transistor BT23 are placed in the ON state.
As a result, the drain for memory cell transistor M2 is connected to metal wire ML3 (main bit line D2) via MOS transistor BT11. In addition, the source of memory cell transistor M2 is connected to metal wire ML2 (virtual main grounding line V2 which assumes grounding potential GND) via MOS transistor BT13.
Next, X decoder 4 sets word line WD2 to [H] level in accordance with the data in address AD for selecting cell transistor M2. As a result, all memory cell transistors for which the gate is connected to word line WD2 are placed in the ON state, these including memory cell transistor M0, memory cell transistor M1, memory cell transistor M2 and memory cell transistor M3.
However, the source and drain for the memory cell transistor positioned to the left of virtual sub-grounding line B13 which is connected to the memory cell transistor M2 source, i.e., to which metal wire ML2 (virtual main grounding line V2), which becomes the grounding potential GND, is connected, enter the OPEN state. For this reason, the current flows via virtual sub-grounding line B13 from the source of memory cell transistor M1 into metal wire ML2 (virtual main grounding line V2) only.
The source and drain for the memory cell transistor positioned to the right of sub-bit line B11 which is connected to the drain of memory cell transistor M2, i.e., to which metal wire ML3 (main bit line D2), connected to sense amplifier circuit 9, is connected, become a specific potential Vp. For this reason, the current that flows from metal wire ML3 (main bit line D2), which is connected to sense amplifier circuit 9, flows into the drain of memory cell transistor M2 only.
As described above, in accordance with the data in address AD for selecting memory cell transistor M2, Y decoder 12, bank decoder 13, Y selector 17 and virtual GND selector 15 operate so that the current from sense amplifier circuit 9 flows into memory cell transistor M2 only. As a result, the data stored in memory cell transistor M2 is accurately read out.
d. Fourth Impression Pattern (Read Out of Memory Cell Transistor M3)
In order to sense the current flowing to memory cell transistor M3, the following impression pattern is established so that current does not flow to other memory cell transistors from metal wire ML3 (main bit line D2) that is connected to sense amplifier circuit 9.
For example, as shown in FIG. 18, based on Y decoder signal YD input from Y decoder 12 in accordance with the data in address AD for selecting cell transistor M3, Y selector 17 places metal wire ML5 (main bit line D3) in the OPEN state, and connects metal wire ML3 (main bit line D2) and sense amplifier circuit 9. In addition, similarly, the Y sector impresses a specific bias voltage Vp onto metal wire ML1 (main bit line D1) based on Y decoder signal YD.
Then, in accordance with the data in address AD for selecting cell transistor M3, virtual GND selector 15 places metal wire ML0 (virtual main grounding line V1) in the OPEN state, designates metal wire ML4 (virtual main grounding line V3) as grounding potential GND, and sets metal wire ML2 (virtual main grounding line V2) to a specific bias voltage Vp.
In accordance with the data in address AD for selecting cell transistor M3, bank decoder 13 sets bank selection signal BS1 and bank selection signal BS2 to [H] level. As a result, MOS transistor BT01, MOS transistor BT11, MOS transistor BT21, MOS transistor BT02, MOS transistor BT12 and MOS transistor BT22 enter the ON state.
As a result, the drain for memory cell transistor M3 is connected to metal wire ML3 (main bit line D2) via MOS transistor BT11. In addition, the source of memory cell transistor M3 is connected to metal wire ML4 (virtual grounding line V3 which becomes grounding potential GND) via MOS transistor BT12.
Next, X decoder 4 sets word line WD2 to [H] level in accordance with address AD data for selecting cell transistor M3. As a result, all memory cell transistors for which the gate is connected to word line WD2 are placed in the ON state, these including memory cell transistor M0, memory cell transistor M1, memory cell transistor M2 and memory cell transistor M3.
However, the source and drain for the memory cell transistor positioned to the right with respect to virtual sub-grounding line B22 which is connected to the source of memory cell transistor M3, i.e., to which metal wire ML4 (virtual main grounding line V3), which becomes the grounding potential GND, is connected, are placed in the OPEN state. For this reason, current flows from the source of memory cell transistor M3 via virtual sub-grounding line B22 to metal wire ML4 only.
The source and drain for the memory cell transistor positioned to the left of sub-bit line B11 which is connected to the drain of memory cell transistor M3, i.e., to which metal wire ML3 (main bit line D2), connected to sense amplifier circuit 9, is connected, become a specific potential Vp. For this reason, the current that flows from metal wire ML3 (main bit line D2) which is connected to sense amplifier circuit 9 flows into the drain of memory cell transistor M3 only.
The source and the drain for the memory cell transistor that is positioned to the left with respect to sub-bit line B01 to which metal wire ML1 (main bit line D1) is connected enter the OPEN state. Accordingly, current does not flow from metal wire ML1 (main bit line D1).
As described above, in accordance with address AD data for selecting memory cell transistor M3, Y decoder 12, bank decoder 13, Y selector 17 and virtual GND selector 15 operate so that the current from sense amplifier circuit 9 flows into memory cell transistor M3 only. As a result, the data stored in memory cell transistor M3 is accurately read out.
However, crosstalk noise may or may not be superimposed on metal wire ML3 (main bit line D2) in the above-described semiconductor memory device impression patterns, depending upon the voltage impression states of metal wire ML4 and metal wire ML2 which are adjacent to the metal wire ML3 (main bit line D2) that is connected to and being sensed by sense amplifier circuit 9.
Such presence and absence of crosstalk noise causes the negative effect of delaying the access time. This is because time is required for the output from sense amplifier circuit 9 to become the actual data stored in the memory cell transistor, and this time depending upon the voltage level setting for the reference signal RG that is supplied from reference circuit 10 to sense amplifier circuit 9. (In other words, the voltage level of the reference signal RG should be set in consideration of crosstalk noise, so that the access time is delayed if the voltage level is not set appropriately.)
Reference transistors are provided within reference circuit 10 for each of word selection line WD1.about.word selection line WDn which have the same design as the memory cell transistors inside memory cell array 16B (see FIG. 13). Threshold values are adjusted in these reference transistors so that, when ON, the output from bias circuit 101 assumes a potential level that is intermediate for the memory cell transistors inside memory cell array 16B in which [H] and [L] data are stored.
The source of this reference transistor is grounded, and its drain is connected to sense amplifier circuit 9. Reference signal RG is output to sense amplifier circuit 9. In addition, in order to provide the reference transistor source and drain with the same characteristics as the memory cell transistor of memory cell array 16B, it is acceptable to insert a MOS transistor for forming Y selector 17, bank selector 16A, bank selector 16C and virtual GND selector 15.
Next, test results using a simulation (SPICE: Simulation Program with Integrated Circuit Emphasis) will be used to explain the reason why the access time is delayed due to crosstalk noise on metal wire ML3 (main bit line D2) from adjacent metal wire ML2 and metal wire ML4.
The voltage amplifying circuit to which metal wire ML3 (main bit line D2) is connected by Y selector 17 that is employed in this simulation will be explained using FIG. 19. FIG. 19 is a circuit diagram showing the structure of bias circuit 100 that is provided inside sense amplifier circuit 9 (see FIG. 13).
In this figure, M1 is a p-channel MOS transistor in which the source is connected to a power source Vcc. The gate is connected to terminal T1 and the drain is connected to the source of MOS transistor M2.
MOS transistor M2 is a p-channel MOS transistor. The gate is connected to terminal T3 and the drain is connected to the drain of MOS transistor M3. MOS transistor M3 is an n-channel MOS transistor. The gate is connected to terminal T3 and the source is grounded. M4 is an n-channel MOS transistor in which the source is grounded. The gate is connected to terminal T1 and the drain is connected to the drain of the MOS transistor M3.
M5 is a p-channel MOS transistor. The source is connected to electric source Vcc, and the gate and drain are connected to terminal T2. M6 is an n-channel MOS transistor. The drain is connected to terminal T3, the gate is connected to the drain of MOS transistor M3, and the source is connected to terminal T3.
When control signal SEB input from terminal T1 is at [H] level, MOS transistor M1 enters the OFF state and MOS transistor M4 enters the ON state. As a result, signal S becomes [L] level. Accordingly, MOS transistor M6 enters the OFF state, and the main bit line connected via Y selector 17 enters an OPEN state with sense amplifier circuit 9. Accordingly, the output signal Dout that is output from terminal T2 becomes [H] level (electric source Vcc).
In contrast, when control signal SEB input from terminal T1 is at [L] level, MOS transistor M1 enters the ON state and MOS transistor M4 enters the OFF state. As a result, signal S becomes [H] level. Accordingly, MOS transistor M6 enters the ON state, and the main bit line connected via Y selector 17 is connected to sense amplifier circuit 9. Accordingly, with regard to the output signal Dout that is output from transistor terminal T2, an output signal Vout having a voltage in accordance with the threshold of the memory cell transistor that is connected to the main bit line that is connected via Y selector 17 is output to a differential amplifying circuit.
At the same time, inside reference circuit 10, the reference transistor in which a word selection line in the same row as the memory cell transistor selected corresponding to address signal AD is connected to the gate, enters the ON state. Reference signal DG is input into another bias circuit 101 that has the same structure as bias circuit 100 inside sense amplifier circuit 9. The differential amplifying circuit provided within sense amplifier circuit 9 compares voltage Vd of output signal Dout outputted by bias circuit 100 and the amplified voltage level of reference signal DG from reference circuit 10 that was output from the other bias circuit 101.
An [H]/[L] detection of the data stored in the memory transistor is performed in the results of this comparison. For example, when voltage Vd is larger than the voltage level of the output from the other bias circuit 101, then the data stored in the memory cell transistor is [H]. Conversely, when voltage Vd is smaller than the voltage level of the output from the other bias circuit 101, then the data stored in the memory cell transistor is [L].
Accordingly, if a simulation is performed of the relative relationship over time between this voltage Vd and the voltage level of reference signal DG, then a judgment can be made of the extent to which crosstalk noise from adjacent metal wire ML2 and metal wire ML4 is effecting metal wire ML3 (main bit line D2).
Next, a diagram of the results of the simulation will be used to explain the action for reading out the data stored in a conventional semiconductor memory device memory cell transistor. The explanation will be carried out referring to FIGS. 13, 14 and 19 in sequence. FIG. 20 is a diagram showing the results obtained when the action for reading out the data stored in the memory cell transistor is simulated using SPICE. In this figure, the voltage level is shown on the vertical axis, while time is shown on the horizontal axis (where 1 dot=1 ns).
In this figure, line L2 shows the voltage level of output signal Dout from bias circuit 100 in the data read out from a memory cell transistor in which [H] data is stored, when the voltage impression pattern on metal wire ML0.about.metal wire ML5 shown in FIGS. 15, 17, and 18 is voltage impression pattern 1. Line L1 shows the voltage level of output signal Dout from bias circuit 100 in the data read out from a memory cell transistor in which [H] data is stored, when the voltage impression pattern on metal wire ML0.about.metal wire ML5 shown in FIG. 16 is voltage impression pattern 2.
Line LA shows the voltage level of output signal Dout from bias circuit 100 in the data read out from a memory cell transistor in which [L] data is stored, when the voltage impression pattern on metal wire ML0.about.metal wire ML5 shown in FIGS. 15, 17, and 18 is voltage impression pattern 1. Line L3 shows the voltage level of output signal Dout from bias circuit 100 in the data read out from a memory cell transistor in which [L] data is stored, when the voltage impression pattern on metal wire ML0.about.metal wire ML5 shown in FIG. 16 is voltage impression pattern 2.
Similarly, line L2 shows the voltage level of metal wire ML3 (main bit line D2) that is connected to a memory cell transistor in which [H] data is stored, when the voltage impression pattern on metal wire ML0.about.metal wire ML5 shown in FIGS. 15, 17 and 18 is voltage impression pattern 1.
Line L4 shows the voltage level of metal wire ML3 (main bit line D2) that is connected to a memory cell transistor in which [L] data is stored, when the voltage impression pattern on metal wire ML0.about.metal wire ML5 shown in FIGS. 15, 17 and 18 is voltage impression pattern 1. Line L3 shows the voltage level of metal wire ML3 (main bit line D2) that is connected to a memory cell transistor in which [L] data is stored, when the voltage impression pattern on metal wire ML0.about.metal wire ML5 shown in FIG. 16 is voltage impression pattern 2.
At time t10 (210 ns), address signal AD is input from an external circuit, and sense amplifier circuit 9 and a precharge circuit are activated by the signal from an address signal detecting circuit not shown in the figures. In other words, the control signal SEB input from an address signal detecting circuit, not shown in the figures, to terminal T1 of the aforementioned bias circuit 100 (FIG. 19) in sense amplifier circuit 9, becomes [L] level, and a specific bias voltage Vp is output to Y selector 17 via terminal T3. Similarly, precharge circuit 8 outputs a precharge signal PC to the Y selector.
Next, at time t11 (215 ns), Y decoder 12 decodes the address signal AD that was inputted and held in address buffer 11, and outputs Y selector signal YG to Y selector 17. Y selector 17 reads out memory cell transistor M0, for example, based on the input Y selector signal YG, and, as shown by the voltage impression pattern on metal wire ML0.about.metal wire ML5 in FIG. 15, initiates a charge by providing a specific bias voltage Vp from sense amplifier circuit 9 to metal wire ML3 (main bit line D2), and initiates a charge by applying the precharge signal PC from precharge circuit 8 onto metal wire ML5 (main bit line D3). As a result, metal wire ML1 (main bit line D1) is placed in the OPEN state.
Similarly, based on input address signal AD, virtual GND selector 15 initiates a charge by applying a specific bias voltage Vp to metal wire ML4 (virtual main grounding line V3), and grounds metal wire ML2 (virtual main grounding line V2), for example, as shown by the voltage impression pattern on metal wire ML0.about.metal wire ML5 in FIG. 15. As a result, metal wire ML0 (virtual main grounding line V1) is placed in the OPEN state. As a result, metal wire ML3 (main bit line D2) is adjacent to metal wire ML2 (virtual main grounding line V2), which has a specific bias voltage Vp, and grounded metal wire ML4 (virtual main grounding line V3) (first impression pattern, third impression pattern, and fourth impression pattern).
As a result, the voltage levels of line L1.about.line L4, i.e., the potential of metal wire ML3 (main bit line D2), start to rise. Simultaneously, the voltage level of line L1.about.line L4, i.e., the voltage level of the output signal Dout outputted from bias circuit 100, gradually decreases since current is supplied to metal wire ML3 (main bit line D2).
Next, at time t12 (218 ns), based on address signal AD, bank recoder 13 outputs bank selection signal BS0 and bank selection signal BS2 to bank selector 16A at [H] level, and outputs bank selection signal BS1 and bank selection signal BS3 at [L] level to bank selector 16C.
As a result, metal wire ML0 (virtual main grounding line V1) is connected to virtual sub-grounding line B02, metal wire ML1 (main bit line D1) is connected to sub-bit line B00, metal wire ML2 (virtual main grounding line V2) is connected to virtual sub-grounding line B12, metal wire ML3 (main bit line D2) is connected to sub-bit line B10, metal wire ML4 (virtual main grounding line V3) is connected to virtual sub-grounding line B22, and metal wire ML5 (main bit line D3) is connected to sub-bit line B20. The precharge on metal wire ML3 (main bit line D2) from bias circuit 100 is terminated, and the voltage level of output signal Dout and the voltage level of metal wire ML3 (main bit line D2) starts to rise due to the supply of current from electrical source Vcc.
Next, at time t13 (222 ns), based on address signal AD, X decoder 4 sets the word selection line WD2 to [H] level. Memory cell transistor M0 is selected and the data stored in memory cell transistor M0 is read out. Bias circuit 100 shows the change in line L1 if [H] data is written in the memory cell transistor, and shows the change in line L3 if [L] data is written in the memory cell transistor.
Next, at time t14 (231 ns), a comparison with the reference voltage level is enabled at a differential amplifying circuit in sense amplifier circuit 9. In other words, this differential amplifying circuit begins sensing the current flowing to memory cell transistor M0. As a result, the [H]/[L] detection of the data stored in memory cell transistor M0 is enabled.
Next, at time t15 (236 ns), the voltage level of reference signal RG and the voltage level of metal wire ML3 (main bit line D2) assume a difference at which a comparison is possible. Sense amplifier circuit 9 outputs the results of the [H]/[L] detection for the data stored in memory cell transistor M0. In FIG. 20, time t15 is [236 ns].
Next, when reading out memory cell transistor M1, a charge is initiated by applying a specific bias voltage Vp from sense amplifier circuit 9 to metal wire ML3 (main bit line D2), and a charge is initiated by applying the precharge signal PC from precharge circuit 8 to metal wire ML1 (main bit line D1), as shown by the voltage impression pattern on metal wire ML0.about.metal wire ML5 in FIG. 16. As a result, metal wire ML5 (main bit line D3) is placed in the OPEN state.
Similarly, based on the input address signal AD, virtual GND selector 15 initiates a charge by applying a specific bias voltage Vp to metal wire ML0 (virtual main grounding line V1), and grounds metal wire ML2 (virtual main grounding line V2), for example, as shown by the voltage impression pattern on metal wire ML0.about.metal wire ML5 in FIG. 16. Metal wire ML4 (virtual main grounding line V3) is thereby placed in the OPEN state. As a result, metal wire ML3 (main bit line D2) is adjacent to metal wire ML4 (virtual main grounding line V3), which is OPEN, and metal wire ML2 (virtual main grounding line V2), which is grounded (second impression pattern).
At time t3 (222 ns), based on address signal AD, X decoder 4 sets the word selection line WD2 to [H] level. Memory cell transistor M1 is selected and the data stored in memory cell transistor M1 is read out. The output signal Dout of bias circuit 100 shows the change in line L2 assuming [H] data is written in the memory cell transistor, and shows the change in line L4 assuming [L] data is written.
In the second impression pattern in FIG. 20, metal wire ML4 (virtual main grounding line V3) which is adjacent to metal wire ML3 (main bit line D2), is in the OPEN state, and metal wire ML2 (virtual main grounding line V2) is grounded. As a result, metal wire ML3 (main bit line D2) is not affected by crosstalk noise from its neighboring metal wire. Thus, the output of bias circuit 100 assumes the change shown by line L3 if [L] data has been written in, and assumes the change shown by line L1 if [H] data has been written in.
Conversely, in the first, third and fourth impression patterns in FIG. 20, metal wire ML4 (virtual main grounding line V3), which is adjacent to metal wire ML3 (main bit line D2), is at a specific bias voltage Vp, and metal wire ML2 (virtual main grounding line V2) is grounded. For this reason, metal wire ML3 (main bit line D2) is affected by crosstalk from the adjacent metal wire ML4 (virtual main grounding line V3), and assumes the change shown by line L4 if [L] data is written in and the change shown by line L2 if [H] data is written.
Area ZM in FIG. 20 has been enlarged and is shown in FIG. 21 in order to facilitate understanding of the change over time in metal wire ML3 (main bit line D2) when [L] data and when [H] data are written in, in the first, third and fourth impression patterns, and in the second impression pattern, respectively. Voltage is shown on the vertical axis and time is shown on the horizontal axis.
In this figure, line L2 shows the change over time in metal wire ML3 (main bit line D2) when [H] data is written in in the first, third and fourth impression patterns. Line L1 shows the change in time in metal wire ML3 (main bit line D2) when [H] data is written in in the second impression pattern.
Line L4 shows the change over time in metal wire ML3 (main bit line D2) when [L] data is written in in the first, third and fourth impression patterns. Line L3 shows the change over time in metal wire ML3 (main bit line D2) when [L] data is written in in the second impression pattern.
In other words, in FIG. 21, when the potential of metal wire ML3 (main bit line D2) is rising, the adjacent metal wire ML4 (virtual main grounding line V3) also rises toward the specific bias voltage Vp. Thus, due to the coupling capacity between metal wire ML3 (main bit line D2) and metal wire ML4 (virtual main grounding line V3), a mutual crosstalk noise effect results. For this reason, the output of bias circuit 100 becomes a value that is elevated as a result of the crosstalk noise effect on metal wire ML3 (main bit line D2). Thus, the value shown by line LL2 and line LL4 assumes a high value with respect to line LL1 and line LL3 for the first impression pattern, third impression pattern and fourth impression pattern respectively. As a result, the output signal Dout of bias circuit 100 is affected by crosstalk noise, and assumes the result shown in FIG. 20.
Accordingly, in the conventional semiconductor memory device, the voltage change in metal wire ML3 (main bit line D2) differs between the first, third, and fourth impression patterns and the second impression pattern. For this reason, it is not possible to simply set the reference voltage level output from bias circuit 101 to a value that is intermediate between the case where the data stored in the memory cell transistor is [H] and the case where the data stored in the memory cell transistor is [L]. As a result, the conventional semiconductor memory device has a disadvantage in that a fast read out access time cannot be achieved if an optimal value is not set for all the output states of bias circuit 100.
The reference optimal value that is output by bias circuit 101 at this time is in between line L1 in which [H] is the minimum value for the data stored in the memory cell transistor and line L4 in which [L] is the maximal value for the data stored in the memory cell transistor. However, because the threshold value of the reference transistor formed by reference circuit 10 deviates because of effects imparted during the manufacturing process, the potential difference between line L1 and line L4 when a comparison state is enabled at sense amplifier circuit 9 is not a large value. Accordingly, the margin for setting the reference intermediate between line L1 and line L4 is extremely small.
In the conventional semiconductor memory device described above, the voltage level of reference signal RG from reference circuit 10 is set to a value that can correspond to the voltage of output signal Dout of bias circuit 100 based on the voltage level of signal DG metal wire ML3 (main bit line D2) for both the case of the first, third and fourth impression patterns, and the case of the second impression pattern.
For this reason, in the conventional semiconductor memory device, the access time for read out from the memory cell transistor in which the same data is stored differs between the first, third and fourth impression patterns, and the second impression pattern. Thus, the conventional semiconductor memory device is problematic in that the least optimal value from among the plurality of access times becomes the access time for the semiconductor memory device.
In addition, in the conventional semiconductor memory device, the voltage level of reference signal RG corresponds to a plurality of states for metal wire ML3 (main bit line D2), so that the aforementioned access time differs greatly depending on the threshold voltage of the transistor that determines the values of the data stored in the memory cell transistor. Accordingly, the deviation in the threshold values of the memory cell transistor also causes a reduction in the margin for setting the reference voltage level.